Communication arrangement in electrographic printer and copier device

ABSTRACT

A unified bus system is used for communication in a printer or copier apparatus. Each functional unit of the printer or copier apparatus is connected to the bus by an interface. The interface includes a duel-port RAM memory unit in which data messages associated with the specific functional unit or sensors in the printer or copier apparatus are stored. The functional units are notified of the presence of new data or messages on demand so that each functional unit has an overall picture of the functional status of the printer or copier.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is directed to a communication means in anelectrographic printer or copier device. A plurality of function unitssuch as a fixing station, a character generator, a paper transportmeans, a central control unit, etc., are contained in an electrographicprinter or copier device. Over and above this, there are numeroussmaller function units such as, for example, sensors, motors, switches,keys, etc. The functionality of all of these function units must becoordinated for the operation of the printer or copier device.

2. Description of the Related Art

Bus systems that are controlled via a main module HM are utilized inknown printer or copier devices for the coordination of approximately100 sensors and approximately 40 power consuming units. The structure ofsuch a known control system may be seen from FIG. 1. The signaltransmission between the main module HM and the sub-modules SUB1 . . .SUBn ensues via a first bus system BBUS. One sub-module SUB1 . . . SUBncontrols power consumers LV, acquires data from sensors, and exchangesdata and messages with other sub-modules SUB1 . . . SUBn. The powerconsumers LV are directly controlled by the sub-modules SUB1 . . . SUBnvia individual lines, and sensor assemblies SPU1 . . . SPUn for editingthe information acquired by the sensors are inserted between thesub-module SUB1 . . . SUBn and individual sensors ES. The sub-modulesSUB1 . . . SUBn communicate with the sensor assemblies via second bussystem VBUS. The second bus system VBUS can, for example, be a couplingwith a parallel V24 interface. The communication between the sensorassemblies and the sub-modules ensues on the basis of what is referredto as a polling method wherein a submodule SUB1 . . . SUBn interrogatesdesired data from a sensor assembly SPU1 . . . SPUn. The communicationbetween the sub-modules SUB1 . . . SUBn also ensues according to thispolling method, whereby the main module HM can be viewed as a master andthe sub-modules SUB1 . . . SUBn can be viewed as slaves.

The data traffic between the individual sub-modules SUB1 . . . SUBn canthereby only be sequenced in dialog traffic between the sub-modules SUB1. . . SUBn and the main module HM. This, for example, means that amessage of a sensor ES to a sub-module SUBn must be communicated fromthis sub-module SUBn to the main module HM and from the latter to theother sub-module SUB1 . . . SUB3. Over and above this, synchronouscontrol commands can only be transmitted asynchronously to theindividual submodules SUB1 . . . SUBn.

In addition to the long program running time, the known interrogationmethod also causes an increased wiring outlay since parallel wiring isrequired. The efficiency of the interrogation method is also low becauseconditions that have not changed since the preceding interrogation arefrequently interrogated. The data traffic, which can only be sequencedbetween the master and slave, is coordinated with a priority control bya single control unit contained in the main module HM. Delays in thefunction execution of the printer or copier device can thus occur. Thisfact is countered in that fast signal changes are handled with what isreferred to as a parallel port interrogation.

SUMMARY OF THE INVENTION

The present invention is based on the object of providing acommunication means and a communication method for an electrographicprinter or copier device that assures a fast, delay-free communicationwhich at the same time requires little outlay for wiring and provides ahigh dependability.

This and other objects and advantages of the invention are achieved by acommunication means in an electrographic and copier device having aplurality of function units that are coupled to one another for datacommunication that includes a coupling of the function units with auniform bus system, an interface to the bus system allocated to eachfunction unit that contains a memory unit with random access in whichspecific information respective to the function units can be depositedin defined address areas, and these information are continuously updatedin all interfaces by the bus system so that each function unit has anoverall picture of the function statuses in the electrographic printerand copier device available to it all the time.

The present invention also provides a method for communication in anelectrographic printer and copier device between a plurality of functionunits that are coupled to one another by a uniform bus system for datacommunication, the method including the steps of: given aninitialization, interfaces to the bus system that are allocated to eachfunction unit are placed into a basic condition so that the basiccondition data of all function units are available in address areasrespectively defined therefor in a memory unit with random access thatis contained in each interface; upon occurrence of a change of acondition of a function unit, this change is entered in the effectedmemory area of the memory unit that is allocated to the function unit;and this change is transmitted with the bus system to the interfaces ofall function units and is respectively deposited thereat in the effectedaddress area of the memory unit, so that each function unit has anoverall picture of the function conditions in the electrographic printerand copier device available to it all the time.

Particular developments and improvements of the invention are providedby a message-oriented system that immediately communicates modificationof information to all function units.

In one embodiment, a memory unit that is a dual port RAM is provided ineach function unit, the address area of the memory being divided intotwo individual areas, whereby the first address area serves foraccepting data and messages and the second address area serves foraccepting information with respect to the data and messages deposited inthe first address area.

The communication apparatus provides an allocation of a respective dataor message block to an information block so that the addresses of therespectively first byte of the blocks have a specific address spacingfrom one another.

Two first-in-first-out registers are preferably allocated to theinterface, whereof one can be written at the bus side and read at thefunction unit side and the other can be written and read in the oppositedirection; the address of a data or message block and the length thereofin the memory unit can be entered into these FIFOs with random access,and the read out of these information starts an interrupt routine in thereading processor.

A further interface to the bus system can be utilized for couplingfunction units with slight control jobs to the bus system, whereby thefurther interface is configured such that it only allows data andmessages destined for the respective function unit to pass.

In the method, a memory unit fashioned as what is referred to as a dualport RAM is provided in each function unit, the address area thereofbeing divided into two individual areas, whereby, given a change of acondition of a function unit, data and messages are entered in the firstaddress area and information with respect to the data and messagesdeposited in the first address area are entered into the second addressarea.

Two first-in-first-out registers are allocated to the interface, whereofone can be written at the bus side and read at the function unit sideand the other can be written and read in the opposite direction,whereby, dependent on the information deposited in the memory unit withrespect to data and messages to be modified, the address of a data ormessage block and the length thereof is entered into the respectivelyeffected FIFO and the read-out of this information starts an interruptroutine in the reading processor.

Due to the inventive employment of a uniform bus system that couples thefunction units to one another for data communication, a data exchangewill always ensue directly between the function units. Each interface ofa function unit can thereby be viewed as a master, for which reason thecommunication occurs only between masters. As a result of the definedaddress areas in the memory units of the interfaces, which are alwaysupdated by the bus system, every function unit always has the currentinformation in the printer or copier device available to it. Acomplicated requesting of information by an interface defined as a slavefrom the master is eliminated. An inquiry by a function unit about thecondition of other function units ensues by simple access to its ownmemory unit of the interface. This requires comparatively little time,as a result whereof the function unit is only slightly loaded by thecommunication relationship to the other function units.

According to a development and improvement of the invention, the memoryunit of the interface is fashioned as a dual port RAM. Thisadvantageously allows a simultaneous access on the part of the functionunit and of the bus system to the memory unit. Moreover, the dual portRAM is divided into two address areas wherein, data and messages aredeposited in the first area and information with respect to these dataand messages are deposited in the other area. As a result thereof, therequested data can be designationally accessed. Advantageously, thedistance of the start byte of the data and messages that are allocatedto one that are another from the information is selected in a specificaddress spacing. This facilitates the addressing; particularly when, forexample, a spacing of 2 k/byte, only some other address bits followingaccess to the first block need be modified for the access to theappertaining of the block.

The information with respect to a status of a function unit, forexample, whether a specific motor is operating, is deposited in the dataor message block. Information about the data and message block arecontained in the appertaining information block. This can be anidentifier in accord wherewith this is new information that must betransmitted. It can also be information about the way the information isto be reported from the memory unit to the function unit. Theinformation can be independently called by the function unit (RTR) bit,or an interrupt request brings the presence of new information in thedual port RAM to the attention of the function unit. Since this can bedifferent from function unit to function unit, the information blocks inthe different dual port RAMs can differ from one another. Theinformation blocks can be updated as needed during the printingoperation.

According to a further improvement and development of the invention, twofirst-in-first-out (FIFO) registers are allocated to the memory unit.These FIFO registers have an FIFO-empty line available to them thattriggers an interrupt routine at their allocated reception processor.The address of a data or message block and the length thereof is enteredinto the FIFO registers when the processor entering into the memory unitrecognizes with reference to the information in the information blockthat an interrupt routine is to be initiated. In this way, a receivingprocessor can process the messages and data intended for it when itswork execution allows this. At the other side, the transmittingprocessor can deliver independently of the receiving processorsdependent on the depth of the FIFO, for example, 128 messages.

According to a further development and improvement of the invention,function units that do not carry out any specific control job can alsobe coupled to the bus system by a further interface. For example, suchfunction units serve for sensor acquisition and evaluation. Thesefunction units only receive information intended for them. The otherinformation are blanked out by the interface. As a result of thisdevelopment, simple function units can be directly coupled to the bussystem with little outlay. A loading of the other function units due todirect coupling of the simple function units to them is eliminated.

BRIEF DESCRIPTION OF THE DRAWINGS

An example of the invention is explained in greater detail below withreference to the Figures.

FIG. 1 is a block diagram of a communication means according to theprior art;

FIG. 2 is an inventive communication means in block presentation offunction modules that are coupled to one another by a bus system;

FIG. 3 is a simplified interface arrangement in block presentation withmessage filters;

FIG. 4 is an interface arrangement in block presentation with dual portRAM and FIFO registers; and

FIG. 5 is a schematic illustration of a dual port RAM divided into twomemory areas.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Eight function units SUB, SPU of a printer and copier device are shownin the communication means according to FIG. 2. All function units SPUxand SUBx are coupled to one another for communication by a uniform bussystem CANBUS. The sub-modules SUB1 . . . SUBn form a first group offunction units. These sub-modules SUB1 . . . SUBn are, for example, thesubmodules for control of the paper transport, control of the fixingstation, as well as the central control of the printer or copier device.These sub-modules SUB1 . . . SUBn control the units such as motors,heating devices and other power consumers LV that are allocated to themon the basis of sensor elements allocated to these units. The otherfunction units are a matter of simple sensor assemblies that controlkeys, switches, display elements, temperature sensors, motors andsensors located outside the sub-modules SUB1 . . . SUBn.

The coupling of these sensor assemblies SPU1 . . . SPUn to the bussystem CANBUS ensues with an interface according to FIG. 3. The sensorassembly SPU1 . . . SPUn has a first microprocessor UP1, for example ofthe type 80C535, available to it that controls and monitors the functionelements allocated to the sensor assembly and outputs occurring messagesto a following controller CONT, for example of the type 82C200, orreceives them. This controller CONT only allows those messages and datafrom the bus system CANBUS to pass that are required for thefunctionability of the sensor assembly SPU1 . . . SPUn. The number ofthese relevant data messages is extremely low, so that the controllerCONT only has a transmission memory and two selectable receptionmemories available to it. The linking of the controller CONT to the bussystem CANBUS ensues via an analog driver module TR of, for example, thetype 82C250. A level matching to the bus system CANBUS ensues in thisdriver module TR.

The data set to be processed by the other interfaces that are allocatedto the sub-modules SUB1 . . . SUBn is significantly larger. FIG. 4 showsan interface that can process these data sets. A second microprocessorUP2 serves for the control of a sub-module SUB1 . . . SUBn. For example,the circuit type 80C167 can be utilized as second microprocessor UP2.This microprocessor UP2 communicates with the bus system CANBUS via amemory unit DPRAM. A third microprocessor UP3 of, for example, thecircuit type 80C535 is utilized for coupling the memory unit DPRAM tothe bus system CANBUS. It communicates with a bus controller BCONT andthe latter communicates with a bus driver BTR. The circuit type 80C200can be utilized as the bus controller BCONT and the circuit type 80C250can be utilized as bus driver BTR. The second and the thirdmicroprocessor UP2 and UP3 communicate directly with the memory unitDPRAM. The memory unit is a dual port RAM DPRAM.

This dual port RAM DPRAM is structured as shown in FIG. 5. The entireaddress area of the dual port RAM DPRAM is divided into address areasAB1 and AB2. An address in the second address area AB2 is therebyallocated to every address in the first address area AB1. The spacing Kbetween the addresses allocated to one another is always the same andamounts, for example, to 2 KBytes. Data and messages are deposited inthe first address area AB1, and information about the data and messagesof the first section AB1 are deposited in the second address area AB2.

The data and messages of the first address area AB1 are structured inblocks. A block one, D1, D2, Dn is identified by a start address and isa maximum of eight bytes long. The second section AB2 is likewisestructured in blocks I1, I2, In. Each block I1, I2, In of the secondaddress area AB2 contains information of the block D1, D2, Dn of thefirst address area AB1 allocated to it. The spacing K of the startaddresses of the blocks D1, I1, . . . Dn, In, of the different sectionsAB1 and AB2 which are related to one another corresponds to the spacingK of the addresses of the different address areas AB1 and AB2 from oneanother.

The information in the second address area AB2 relate to therespectively appertaining data and message block. These information canbe an identifier, in accordance therewith it is new information thatmust be sent. It can also be information about the way in which theinformation is to be reported from the memory unit DPRAM to the functionunit. The information can be independently called by the function unit(RTR bit) or an interrupt request brings the presence of new informationin the dual port RAM DPRAM to the attention of the function unit. Thelength of the data of the appertaining data block in the first addressarea AB1 is also a component part of the information block I1 . . . In.In general, accordingly, it is a matter of information about how thedata and messages D1 . . . Dn are to be further-processed.

When one of the processors UP2 or UP3 enters data or messages D1 . . .Dn into the first address area AB1 of the dual port RAM DPRAM, then, byreading out the corresponding information block I1 . . . In from thedual port RAM DPRAM, it conforms itself of the way in which theprocessor UP2 or UP3 lying opposite should obtain possession of thesedata or messages D1 . . . Dn. When it is a matter of data or messages D1. . . Dn that the processor lying opposite can fetch itself withouthaving to be informed thereof, the data are transmitted in a validfashion by the entry into the first address area AB1. When, however, itproceeds from the information of the second address area AB2 that thereceiving microprocessor UP2 or UP3 is to be informed of the data ormessages D1 . . . Dn by an interrupt routine, then the transmittingprocessor UP2 or UP3 enters the address of the first descriptive byte ofa message in the first address area AB1 and the appertaining data lengthinto a first-in-first-out (FIFO) register FIFO1 or FIFO2. The FIFOregister FIFO1, FIFO2, contains an FIFO empty line that is coupled tothe receiving processor UP2 or UP3 and triggers an interrupt in thereceiving microprocessor UP2 or UP3 dependent on the memory entry in theFIFO register FIFO1 or FIFO2.

Each FIFO register FIFO1 and FIFO2 is responsible for one transmissiondirection. Thus, the first FIFO register FIFO1 is written by the thirdmicroprocessor UP3 and is read by the second microprocessor UP2. Thesecond FIFO register FIFO2 is written by the second microprocessor UP2and read by the third microprocessor UP3. The FIFO registers FIFO1 andFIFO2 can accept 128 different messages that are intended to trigger aninterrupt. These messages can be successively processed withoutmodifying their sequence.

The above-described selection method is advantageous upon reception ofdata by a function unit SUB1 . . . SUBn because the secondmicroprocessor UP2 is only made use of when it is a matter of messagesto be taken immediately into consideration. When, however, the functionunit SUB1 . . . SUBn has generated new data or messages D1 . . . Dn,then these must be immediately available for the other function unitsSUB1 ... SUBn, SPU1 . . . SPUn. Only then is a friction-free functionexecution possible without a waiting time in the printer or copierdevice.

The immediate delivery of data or messages D1 . . . Dn is promoted inthat the second microprocessor UP2 undertakes an entry in the secondFIFO register FIFO2 given the presence of a new message. This ensuesindependently of the information in the second address area AB2 of thedual port RAM DPRAM. The third microprocessor UP3 will thus transmit thedata or message to the other function units SPUx and SUBx via the bussystem CANBUS at the next opportunity.

Since, depending on whether it is a matter of an interface with the dualport RAM or with the controller CONT, the bus interfaces of all functionunits SPU1 . . . SPU3, SUB1 . . . SUBn are identically constructed, acurrent image of all sensors, users and control statuses of the printeror copier device is always available to each function unit SUB1 . . .SUBn, SPU1 . . . SPUn. The allocation of data or messages D1 . . . Dn istherefore especially simple because the same address is allocated tothese data or messages D1 . . . Dn in every dual port RAM DPRAM. Forexample, data or messages D1 . . . Dn to the sensor 1 are depositedunder the start address 100 of a memory DPRAM. After theircommunication, these data or messages D1 . . . Dn are available quasitime-synchronously in all dual port RAMs DPRAM of the other functionunits SUB1 . . . SUBn. They merely have to be read beginning with theaddress 100.

Since information are transmitted over the bus system CANBUS onlymessage-oriented, i.e. only when data or messages D1 . . . Dn change,the data traffic on the bus system CANBUS is reduced to a minimum. A bussystem CANBUS that can be utilized for the above-described communicationjobs is known from the CANBUS specification 2.0, parts A and B of April1994 of the Philips Company.

Although other modifications and changes may be suggested by thoseskilled in the art, it is the intention of the inventors to embodywithin the patent warranted hereon all changes and modifications asreasonably and properly come within the scope of their contribution tothe art.

What is claimed is:
 1. A communication arrangement in an electrographicprinter and copier device having a plurality of function units that arecoupled to one another for data communication, comprising:a uniform bussystem connected between the function units; an interface to the uniformbus system allocated to each of the function units, said interfaceincluding a memory unit with random access in which information specificto respective ones of the function units is deposited in defined addressareas, and these information are continuously updated in all interfacesby the bus system, so that each of said function units has an overallpicture of function statuses in the electrographic printer and copierdevice available to it at all times; and said memory unit is a dual portRAM in each of said function units whose address area is divided intofirst and second individual areas, whereby the first individual areaserves for accepting data and messages and the second individual areaserves for accepting information with respect to the data and messagesdeposited in the first individual area.
 2. A communication arrangementaccording to claim 1, comprising:a message-oriented system thatimmediately communicates a modification of an information to all of saidfunction units.
 3. A communication arrangement according to claim 1,comprising:an allocation of a respective data or message block to aninformation block, so that addresses of a first byte of the blocks havea specific address spacing from one another.
 4. A communicationarrangement according to claim 1, comprising:two first-in-first-outregisters allocated to the interface, whereof one of saidfirst-in-first-out registers is connected to be written at a bus sideand read at a function unit side and the other of saidfirst-in-first-out registers is connected to be written and read in anopposite direction; an address of a data or message block and a lengththereof in the memory unit can be entered into said first-in-first-outregisters with random access, and the read out of these informationstarts an interrupt routine in the reading processor.
 5. A communicationarrangement according to claim 1, comprising:a further interface to thebus system that is connected to be utilized for coupling function unitsto the bus system, whereby the further interface is configured such thatit only allows data and messages destined for a respective function unitto pass.
 6. A method for communication in an electrographic printer andcopier device between a plurality of function units that are coupled toone another by a uniform bus system for data communication, comprisingthe following method steps:given an initialization, placing interfacesto the bus system that are allocated to each function unit into a basiccondition so that the basic condition data of all function units areavailable in address areas respectively defined therefor in a memoryunit with random access that is contained in each interface; uponoccurrence of a change of a condition of a function unit, entering saidchange in the effected memory area of the memory unit that is allocatedto the function unit; transmitting said change with the bus system tothe interfaces of all function units and depositing thereat in theeffected address area of the memory unit, so that each function unit hasan overall picture of function conditions in the electrographic printerand copier device available to it at all times; and said memory unit isa dual port RAM in each of said function units, an address area thereofbeing divided into two individual areas, whereby, given a change of acondition of a function unit, data and messages are entered in a firstof said individual areas and information with respect to the data andmessages deposited in the first individual address area are entered intothe second of said individual areas.
 7. A method for communicationaccording to claim 6, comprising the step of:two first-in-first-outregisters allocated to the interface, whereof one of saidfirst-in-first-out registers is connected to be written at a bus sideand read at a function unit side and the other of saidfirst-in-first-out registers is connected to be written and read in anopposite direction, whereby, dependent on information deposited in thememory unit with respect to data and messages to be modified, an addressof a data or message block and a length thereof is entered into arespectively effected one of said first-in-first-out registers andread-out of this information starts an interrupt routine in the readingprocessor.